Technical Article

A 3-Bit Load-Pulling Digital Power Amplifier

This article describes the design of an RF 3-bit digital power amplifier (DPA) using the Cadence® AWR Design Environment® platform. The three amplifiers were designed for different output powers (POUT) and the transmission line (TL) network allows them to load pull one other to achieve eight different amplitude states by alternatively enabling and disabling the amplifiers via their gate bias. A prototype for 500 MHz was designed using Microwave Office® circuit design software with the aid of a genetic algorithm to optimize the TL network for all seven active (on-) states. The optimizer efficiency goals were based on data derived from load-pull simulation.

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