Summit Semiconductor Cuts the Design time for 10GHz Phase Shifter and Low Noise Amplifier Products in Half with Analog Office
Design Challenge at Summit Semiconductor
Summit Semiconductor, a design services company under contract to develop 10GHz phase shifter and low-noise amplifier products for a major customer in the wireless marketplace, had several design challenges. This complicated new IC chip set was an important new product line for the customer.
The phase shifters were critical for beam steering functions in phased-array radar and commercial communication systems. The low-noise amplifiers provide gain blocks with moderate noise figure. The frequency range, along with noise and gain specification, required accurate device and transmission line models for circuit simulation in both time and frequency domains. In addition to the challenges of line and inductor coupling, electromagnetic (EM), skin effect, and interconnect coupling and extraction, there were issues with having a dense layout tightly coupled with the circuit implementation.
The design environment had to be simple, user-friendly, and intuitive, yet support all the design functionalities and features required to tape out on an accelerated schedule. In order to meet the architecture, circuit design, layout, and physical verification challenges, the design environment had to be comprehensive, could not require a major CAD support team, and had to provide interfaces to third-party design tools.
AWR’s Analog Office software, with its ease-of-use, accurate device models, and fully integrated design environment with advanced layout and simulation capabilities tied together with the schematic, helped the Summit Semiconductor design team to significantly reduce its design cycle time. The team was able to go from specification to tapeout in half the time.
The ability to perform “on-the-fly” extraction at any point in the design cycle enabled the design team to accurately simulate interconnect parasitics along with line coupling physical effects early in the circuit design phase. This methodology coupled with utilizing the optimization and tuning capabilities enabled the Summit design team to develop the best topology for its circuit and matching layout.
The ability to mix and match a variety of simulation techniques on different parts of the circuitry provided better analysis of the behaviors of the transmission lines. With AWR’s unique unified data model, the typical seven-to-eight-week timeframe for designing the layout was cut to only three weeks. The verification-to-foundry design checks were performed using the Analog Office design rule check (DRC) interface, which highlights errors in the layout itself, enabling correction early in the process and saving design time.
*Summit Semi is Rick's former company and not to be confused with Summit Semiconductor of recent incorporation. Follow Rick at his new venture of: MPT / Microwave Packaging Technologies
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