Application Note

AXIEM EM Simulator Within Cadence Virtuoso RF for RFIC/SiP Design

A new NI AWR software application note describes an integrated solution in which the AXIEM EM simulator and Cadence Virtuoso provide designers with an IC and package/module design flow that eliminates design failures by using a single golden schematic for simulation, LVS, and EM analysis and verification, without the need for unique schematics for EM and LVS.