Analog Office software offers designers of RF and analog ICs an intuitive, flexible, and accurate design solution. Its unique architecture streamlines designs and increases user productivity by enabling designers to control and integrate best-in-class tools to capture, synthesize, simulate, optimize, lay out, extract, and verify RFIC and analog designs from the system level through to final tapeout.
Seamlessly integrates fully-synchronized schematic/layout design entry with nonlinear circuit analysis and system/electromagnetic (EM) co-simulation for design verification.
RF-aware iNet™ intelligent net and ACE™ automated circuit extraction technologies provide fast interconnect modeling and parasitic extraction of IC structures created with the integrated layout editor.
Supports Cadence Virtuoso RF IP netlist simulation with harmonic balance (HB) simulation for nonlinear, frequency-domain circuit analysis and EM co-simulation for design verification.
Features at a Glance
- Schematic/Layout – Design entry with industry-leading tuning
- APLAC – Linear and nonlinear HB circuit simulation
- Parasitic Extraction – Fully integrated circuit/EM co-simulation with AXIEM™ and Analyst EM simulators
- Load Pull – State-of-the-art load-pull analysis
- Stability – Includes both linear and nonlinear stability analysis
- DRC/LVS – Design rule checking/layout vs. schematic