MMICs That Matter
III-V semiconductor devices offer superior RF performance for mobile devices, communications infrastructure, and aerospace applications. Achieving optimal performance requires reliable circuit simulation, EM verification, communication test benches, and a design flow that links electrical design to physical realization. NI AWR software offers a leading front-to-back monolithic microwave integrated circuit (MMIC) design flow with an innovative user interface and complete integration of design entry, simulation, and physical design tools that enhances engineering productivity and ensures first-pass success.
Design automation accelerates product development with smart workflows for MMIC realization.
Electromagnetic (EM)-enabled process design kits (PDKs) support in-situ parasitic extraction and design verification for enhanced accuracy and greater first-pass success.
An integrated platform supports concurrent electrical and physical design, as well as circuit, system, and EM co-simulation to minimize reliance on multiple point tools.
Design Entry and Management
MMICs integrate active devices within a network of on-chip passive components to provide the functionality necessary for desired performance. Electrical behavior is directly linked to the physical attributes of individual on-chip components, as well as the overall chip layout. A comprehensive MMIC design flow provides parametric, process-specific on-chip component models and layout PCells to support accurate simulations, and a layout that complies with foundry manufacturing rules. Design automation and powerful scripting enables MMIC designers to be more productive by eliminating manual design efforts, excessive data import/export, and supporting tool customization for every special design consideration.
Prior to tapeout, MMIC performance must be verified through computer-aided simulation. RF/microwave electronics rely on specialized measurements such as noise figure (NF) and S-parameters, as well as the nonlinear power, gain compression, and efficiency response to large-signal stimuli. RF simulation uses frequency-domain harmonic-balance (HB) analysis to analyze nonlinear networks, including power amplifiers (PAs) and frequency converters (mixers). With the advent of digital modulation for communications systems, designers may also need to analyze MMICs with circuit-envelop techniques in order to simulate metrics such as adjacent-channel power-ratio (ACPR) and error-vector magnitude (EVM).
Gallium arsenide (GaAs), gallium nitride ( GaN), and silicon germanium (SiGe) semiconductors continue to evolve in support of MMICs operating at higher millimeter-wave (mmWave) frequencies for communications and radar applications, while also offering improved performance across all frequencies. With the advantages of higher bandwidths, greater output power, linearity, and/or NF offered by each new generation of process technologies comes the challenge of accurately representing transistor parasitic, nonlinear, and thermal behaviors in order to provide reliable MMIC simulation. Software vendors must work closely with leading III-V semiconductor foundries and load-pull test system manufacturers to ensure the latest devices offer robust, simulation-ready models for design.
MMIC designers rely on circuit/EM co-simulation, along with RF-aware circuit simulation and frequency-dependent transmission line models, to provide embedded parasitic extraction and design verification. With hierarchical EM/circuit/system co-simulation, designers can perform in-situ EM analysis to capture and correct harmful parasitic couplings and resonances before tapeout. Simulation with pre-configured and/or customized system test benches provides design verification of communications performance metrics such as ACPR, bit-error rate (BER), and EVM for MMICS operating under wireless, standards-specific, modulated waveforms.
The NI AWR Design Environment platform manages the circuit/system/EM components within a project, supporting schematic design entry and fully-synchronized physical design and layout, while seamlessly integrating simulation and design technologies.
Microwave Office circuit design software features APLAC multi-rate, transient, and transient-assisted HB, as well as time-variant (circuit envelope) analysis for linear and nonlinear circuit simulation of PAs and low-noise amplifiers (LNAs). Design aids include load-pull analysis, network synthesis (optional), design for manufacturing (optimization, yield, and statistical analysis), device libraries for printed-circuit board (PCB)-based designs, and PDKs.
The AXIEM 3D proprietary full-wave planar EM simulator is based on method-of-moments (MoM) fast-solver technology that readily analyzes on-chip passive structures such as spiral inductors and metal-insulator-metal (MIM) capacitors, transmission lines, interconnects, vias, and MMIC packaging. Designers can extract S-parameters directly embedded in their MMIC design and visualize fields and currents.
Visual System Simulator™ (VSS) system design software provides virtual test benches that support multiple wireless communications standards for performance metrics such as ACPR, EVM, BER, and complementary cumulative distribution function (CCDF), transmitter conformance testing, and receiver sensitivity analysis. VSS software also offers modulation load-pull analysis for MMIC PA designs and link budget analysis for component specification and system verification.
The Analyst™ simulator with integrated 3D finite-element method (FEM) EM analysis enables designers to model MMIC, package, and board interconnects including wire bonds, air bridges, and ball grids.
PDKs developed to work with NI AWR software are available from leading GaAs, GaN, and silicon foundries.
AWR Connected™ links third-party software/hardware solutions to NI AWR software to provide a more powerful and complete design flow, including layout, EM/thermal analysis, and design-rule checking (DRC)/layout vs. schematic (LVS) technologies.
Network synthesis automatically creates two-port, impedance-matching networks based on proprietary evolutionary EM optimization.