RF modules combine multiple integrated circuits (ICs) into a single package, offering a large amount of functionality in a small space. This level of device integration can be an engineering challenge, requiring design teams to model the electrical behavior of many different technologies, including interconnects (transmission lines) and embedded distributed components, as well as RF, analog, and digital components. Electronic design automation (EDA) software is critical for achieving simulation results that are closely matched to the final results.
Design automation accelerates product development with smart workflows for module realization.
Electromagnetic (EM)-enabled parasitic extraction and design verification provides enhanced accuracy and greater fast-pass success.
The integrated platform supports concurrent electrical and physical design, as well as circuit, system, and EM co-simulation to minimize reliance on multiple point tools.
Design Entry and Management
Companies are shifting their module integration strategies from combining similar building blocks in a single package to the adoption of multifunctional front ends based on diverse technologies to meet the ongoing need for higher performance and reduced component size in multimode and multiband-capable handsets. Module and subsystem designers often use more than one technology in a complete design, including gallium arsenide (GaAs) and gallium nitride (GaN) monolithic microwave ICs (MMICs), silicon (Si) RFICs, and multiple-layer laminates. Each technology is encapsulated in a specific process design kit (PDK) that details the electrical and physical attributes of the manufacturing process and front-end building blocks (component libraries). A multi-technology design flow supporting multiple PDKs and circuit/ EM co-simulation to model bulk-acoustic wave (BAW) and surface-acoustic wave (SAW) filters and multi-layer laminate package is required for comprehensive module analysis and optimization.
Module performance must be verified through computer-aided simulation and analysis. RF/microwave electronics rely on specialized measurements such as noise figure (NF) and small-signal transmission and reflection parameters (S-parameters), as well as their nonlinear power, gain compression, and efficiency response to large-signal stimuli. While transient and time-domain analysis are used for oscillator design and waveform engineering, respectively, most RF simulation is based on frequency-domain, harmonic-balance (HB) analysis, which provides the circuit simulation technology to analyze nonlinear networks, including power amplifiers (PAs) and frequency converters (mixers). With the advent of digital modulation for communications systems, multi-chip modules must be analyzed using circuit envelop in order to simulate metrics such as adjacent-channel power-ratio (ACPR) and error-vector magnitude (EVM).
NI AWR software provides a hierarchical framework that accurately captures the combined electrical performance of diverse IC and substrate laminate process technologies, complex multi-layer interconnects, embedded passives, and surface-mounted devices found in today's multi-chip RF modules used within numerous wireless applications.
Gallium arsenide (GaAs), gallium nitride (GaN), and silicon germanium (SiGe) compound semiconductors continue to evolve in support of MMICs that operate at higher millimeter-wave (mmWave) frequencies for communication and radar applications, while offering improved performance across all frequencies. With the advantages of higher bandwidths, greater output power, linearity, and/or NF offered by each new generation of process technologies comes the challenge of accurately representing transistor parasitic, nonlinear, and thermal behaviors in order to provide reliable MMIC simulation. Software vendors must work closely with leading III-V semiconductor foundries and load-pull test system manufacturers to ensure the latest and greatest semiconductor devices are represented with robust, simulation-ready models for design. In addition, Si RFIC switch, low-noise amplifier (LNA), and PA development are often implemented in Cadence software, which needs to be represented within the module simulation, often in the form of a netlisted intellectual property (IP) block.
Module integrators rely on circuit/EM co-simulation, along with RF-aware circuit simulation and frequency-dependent transmission-line models, to provide embedded parasitic extraction and design verification. Hierarchical EM/circuit/system co-simulation enables designers to perform in-situ EM analysis to capture and correct harmful parasitic couplings and resonances before tapeout. Simulation with pre-configured and/or customized system-test benches provides design verification of communications performance metrics such as ACPR, bit-error rate (BER) and EVM for modules operating under wireless, standards-specific, modulated waveforms.