The demand for wireless connected devices is driving the need for a new generation of high-performance, cost-sensitive silicon products. AWR software provides communications integrated-circuit (IC) designers with a platform to develop complete small-scale RFICs or RF front ends for large-scale RFICs from system- to transistor-level design. The software offers native or third-party schematic/layout entry and fully-integrated electromagnetic (EM) extraction for interconnects and on-chip passive components and enables co-simulation with frequency-domain harmonic balance (HB) and transient time-domain circuit analysis.
Design automation accelerates IP development with smart workflows for RFIC realization.
EM co-simulation provides in-situ extraction and design verification for enhanced accuracy and greater fast-pass success.
HB and circuit-envelope simulation provide frequency-domain analysis of RFICs for communications systems.
Design Entry and Management
RFICs target the high-volume, low-cost transceiver requirements needed for next-generation wireless communications through high-level integration using a single technology. RF complementary metal-oxide semiconductor (CMOS) and silicon germanium (SiGe) semiconductor processes enable IC designers to combine RF, analog, and digital functionality across the RF to millimeter-wave (mmWave) frequency spectrum. A comprehensive RFIC design flow includes parametric, process-specific active, and passive device models for accurate simulation of communications metrics, along with PCells and IC layout support that complies with foundry manufacturing rules. Design automation and powerful scripting enhance designer productivity by eliminating manual efforts and streamlining data import/export between tools and supporting customization.
RFIC performance must be verified through computer-aided simulation prior to tapeout. RF/microwave electronics rely on specialized measurements such as noise figure (NF) and S-parameters, as well as the nonlinear power, gain compression, and efficiency response to large-signal stimuli. RF simulation uses frequency-domain HB to analyze nonlinear networks, including power amplifiers (PAs) and frequency converters (mixers). With the advent of digital modulation for communication systems, designers may also need to analyze RFICs with circuit-envelope techniques in order to simulate metrics such as adjacent-channel power-ratio (ACPR) and error-vector magnitude (EVM).
RF CMOS and SiGe semiconductors continue to evolve in support of higher mmWave frequencies for communications and radar applications, while also offering improved performance across all frequencies. With the advantages of higher bandwidths and greater output power, linearity, and/or NF offered by each new generation of process technologies comes the challenge of accurately representing transistor parasitic, nonlinear, and thermal behaviors in order to provide reliable RFIC simulation.
RFIC designers rely on circuit/EM co-simulation, along with RF-aware circuit simulation and frequency-dependent transmission line models, to provide embedded parasitic extraction and design verification. Using hierarchical EM/circuit/system co-simulation, designers can perform in-situ EM analysis to capture and correct harmful parasitic couplings and resonances before tapeout. Simulation with pre-configured and/or customized system-test benches provides design verification of communications performance metrics operating under wireless, standards-specific, modulated waveforms.
The AWR Design Environment platform provides a single, complete design environment that seamlessly integrates simulation and design technology and manages the circuit/system/EM components within a project, supporting schematic design entry and fully-synchronized physical design and layout.
Analog Office circuit design software features APLAC multi-rate, transient, and transient-assisted HB, as well as time-variant (circuit envelope) analysis for linear and nonlinear circuit simulation of PAs, low-noise amplifiers (LNAs), mixers/frequency converters, filters, switches, and multi-functional monolithic microwave ICs (MMICs). Design aids include load-pull analysis, network synthesis (optional), design for manufacturing (optimization, yield, and statistical analysis), device libraries, and process design kits (PDKs).
The AXIEM 3D proprietary full-wave planar EM simulator is based on method-of-moments (MoM) fast-solver technology that readily analyzes on-chip passive structures such as spiral inductors and metal-insulator-metal (MIM) capacitors, transmission lines, interconnects, vias, and MMIC packaging. Designers can extract S-parameters directly embedded in their MMIC design and visualize fields and currents.
Visual System Simulator™ (VSS) system design software provides virtual test benches that support multiple wireless communications standards for communications performance metrics such as adjacent-channel power-ratio (ACPR), error-vector magnitude (EVM), bit-error rate (BER), and complementary contribution distribution function (CCDF), transmitter conformance testing, and receiver sensitivity analysis. VSS software supports modulation load-pull analysis for MMIC PA designs and link-budget analysis for component specification and system verification.
The Analyst™ simulator with integrated 3D finite-element method (FEM) EM analysis enables designers to model MMIC, package, and board interconnects, including wire bonds, air bridges, and ball grids.
PDKs developed to work with AWR software are available from leading gallium arsenide (GaAs), gallium nitride ( GaN), and silicon silicon (Si) foundries.
AWR Connected™ links third-party software/hardware solutions with AWR software to provide a more powerful and complete design flow, including layout, EM/thermal analysis, and design-rule checking (DRC)/layout vs. schematic (LVS) technologies.
Network synthesis automatically creates two-port, impedance-matching networks based on proprietary evolutionary EM optimization.